Modern multi-threaded processors increasingly experience diminishing performance returns from thread-level parallelism (TLP) due to contention for shared cache resources. While wider cores and increased thread counts are intended to improve throughput, inter-thread cache interference and non-uniform memory access behaviors often negate these benefits, particularly under heterogeneous and dynamically changing workloads. Existing mitigation techniques, including software-managed cache partitioning and architecture-specific control mechanisms, have shown limited scalability and poor portability across platforms.
This thesis investigates adaptive cache management as a means to address these limitations and introduces a Multi-Amdahl–based microarchitectural framework for dynamic cache provisioning. The proposed approach leverages the Multi-Amdahl principle to model how individual thread performance responds to incremental changes in allocated cache capacity, thereby quantifying each thread’s performance sensitivity to cache resources. By continuously estimating these sensitivities at runtime, the proposed mechanism dynamically redistributes cache capacity to maximize overall system throughput while preserving fairness among concurrent threads.
To enable cache resources partitioning, the thesis presents an elastic cache microarchitecture that supports fine-grained, runtime reallocation of cache blocks among threads. This elasticity allows per-thread cache footprints to expand or contract in response to evolving workload demands, enabling effective cache partitioning under constrained resources. The proposed techniques are evaluated using detailed, simulation-based experiments on the SPEC CPU2017 benchmark suite. Results demonstrate performance improvements of up to 23% in instructions per cycle, reductions of up to 74% in cache miss rates, and gains of up to 29% in weighted speedup compared to baseline cache partitioning schemes.
Overall, this work demonstrates that Multi-Amdahl–based modeling provides a practical, scalable foundation for adaptive cache management and offers a viable path toward improving performance and efficiency in future heterogeneous multi-core processor architectures.
MSc seminar. Supervisor: Prof. Uri Weiser and Prof. Freddy Gabbay.
