Colloquia and Seminars

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Computer Science events calendar in HTTP ICS format for of Google calendars, and for Outlook.

Academic Calendar at Technion site.

Upcoming Colloquia & Seminars

  • CS RESEARCH DAY 2018

    CS RESEARCH DAY 2018

    Date:
    Monday, 18.6.2018, 15:00
    Place:
    CS Taub Lobby

    The 8th CS Research Day for graduate studies will be held on Monday, June 18, 2018 between 15:00-17:00, at the lobby of the CS Taub Building.

    Research Day events are opportunity for our graduate students to expose their researches using posters and presentations to CS faculty and all degrees students, Technion distinguished representatives and to high-ranking delegates from the hi-tech leading industry companies in Israel and abroad.

    The participating researches will be on various topics: Cryptology and Cyber, Data Centers and Clouds, Graphics, Intelligent Systems and Scientific Computation, Machine Learning and Information Retrieval, Systems and Applications, Testing and Verification, Theory of Computer Science.

    Participating is free but requires preregistration.

    More details and registration

    Students wishing to present their research are kindly requested to register here.

  • Novel Image and Video Super-Resolution Relying on Denoising Algorithms

    Speaker:
    Alon Brifman, M.Sc. Thesis Seminar
    Date:
    Tuesday, 19.6.2018, 11:00
    Place:
    Taub 601
    Advisor:
    Prof. M. Elad

    Single Image Super-Resolution (SISR) aims to recover a high-resolution image from a given low resolution version of it (the given image is assumed to be a blurred, down- sampled and noisy version of the original image). Video Super Resolution (VSR) targets series of given images, aiming to fuse them to create a higher resolution outcome. Although SISR and VSR seem to have a lot in common, as only the input domain changes between the two, most SISR algorithms do not have a simple extension to VSR, apart for the trivial option of applying the SISR for each frame separately. The VSR task is considered to be a more challenging inverse problem, mainly due to its reliance on a sub-pixel accurate motion estimation, which has no parallel in SISR. Another complication is the dynamics of the video, often addressed by simply generating a single frame instead of a complete output sequence. We suggest an appealing alternative to the above that leads to a simple and robust Super-Resolution framework that can be applied to SISR and then easily extended to VSR. Our work relies on the observation that image and video denoising are well-managed and very effectively treated by a variety of methods, many of which not yet effectively adapted to the super-resolution task. We exploit the Plug-and-Play framework and the recently introduced Regularization-by-Denoising (RED) approach that extends it, and show how to use these denoisers in order to handle the SISR and the VSR problems. This way, we benefit from the effectiveness and efficiency of existing image/video denoising algorithms, while solving much more challenging problems. We test our SISR framework against the NCSR algorithm that solves for denoising and super-resolution separately, and show how its denoiser can be used in order to perform highly effective super-resolution. Then we turn to video, harnessing the VBM3D video denoiser, we compare our results to the ones obtained by the DeepSR and 3DSKR algorithms, showing a tendency to a higher-quality output and a much faster processing.

  • Theory Seminar: On Distributional Collision Resistant Hashing

    Speaker:
    Eylon Yogev (Weizmann Institute of Science)
    Date:
    Wednesday, 20.6.2018, 12:30
    Place:
    Taub 201

    Collision resistant hashing is a fundamental concept that is the basis for many of the important cryptographic primitives and protocols. Collision resistant hashing is a family of compressing functions such that no efficient adversary can find {\em any} collision given a random function in the family.

    In this work we study a relaxation of collision resistance called \emph{distributional} collision resistance, introduced by Dubrov and Ishai (STOC '06). This relaxation of collision resistance only guarantees that no efficient adversary, given a random function in the family, can \emph{sample} a pair $(x,y)$ where $x$ is uniformly random and $y$ is uniformly random conditioned on colliding with $x$.

    Our first result shows that distributional collision resistance can be based on the existence of \emph{multi}-collision resistance hash (with no additional assumptions). Multi-collision resistance is another relaxation of collision resistance which guarantees that an efficient adversary cannot find any tuple of $k>2$ inputs that collide relative to a random function in the family. The construction is non-explicit, non-black-box, and yields an infinitely-often secure family. This partially resolves a question of Berman et al.\ (EUROCRYPT '18). We further observe that in a black-box model such an implication (from multi-collision resistance to distributional collision resistance) does not exist.

    Our second result is a construction of a distributional collision resistant hash from the average-case hardness of SZK. Previously, this assumption was not known to imply any form of collision resistance (other than the ones implied by one-way functions).

    Joint work with Ilan Komargodski.

  • Hardware Security Seminar: Intel SGX keys Management and Trusted Computing Base (TCB) Recovery

    Hardware Security Seminar: Intel SGX keys Management and Trusted Computing Base (TCB) Recovery

    Speaker:
    Ilya Alexandrovich (Intel)
    Date:
    Sunday, 24.6.2018, 09:30
    Place:
    Taub 601

    Bugs, possibly leading to security flaws, are inevitable in the extremely complex modern processors. Some of such bugs may be later fixed in the field by patching processor firmware. In this presentation we will review mechanisms provided by the Intel Software Guard Extensions (SGX) architecture to recover from security vulnerabilities and to re-establish trust in the recovered platform.

    Bio:
    Ilya Alexandrovich is a Principal Engineer in the Intel Core Architecture Group. Since joining Intel eight years ago, he was working on the Intel Software Guard Extensions (SGX) architecture and micro-architecture. Prior to joining Intel he held various senior engineering position at Flash Networks, Lightsand and LanOptics. Ilya holds more than 25 registered patents in the computer security and telecommunications areas. Ilya holds a MSc degree in Physics of Solid State from the Tashkent State Technical University.

  • Real-time Learning using Core-Sets: Autonomous Drones for Rami Levy

    Speaker:
    Dan Feldman - COLLOQUIUM LECTURE
    Date:
    Tuesday, 26.6.2018, 14:30
    Place:
    Room 337 Taub Bld.
    Affiliation:
    Computer Science Dept., Haifa University
    Host:
    Yuval Filmus

    A coreset (or core-set) of a dataset is its semantic compression with respect to a set of classifiers, such that learning the (small) coreset provably yields an approximate classifier of the original (full) dataset. Composable coresets also allow handling streaming and distributed data, e.g. using a cloud or swarm of drones. In this talk I will forge a link between coresets for fundamentals problems in machine (active and deep) learning -- to problems in real-time robotics. Finally, we will see videos of our coreset-based real-time system of autonomous legal, safe and low-cost drones in the supermarket of Rami Levy at Nesher. This is a joint work with Murad Tukan, Elad Tolichensky and Ibrahim Jubran Bio: Dan is a faculty member and the head of the Robotics & Big Data (RBD) Labs in the University of Haifa, after returning from a 3 years post-doc at the Distributed Robotics Lab of MIT, and a previous post-doc the Center for the Mathematics of Information at Caltech. He is known as one of the leading world-wide coresets researchers, mainly for machine learning of Big Data and AI from sensors. In particular, combining computational geometry with applied multidisciplinary science and engineering. This is the main reason of the grants from both government (e.g. NSF-BSF, GIF, Prime Minister Office, Israel Innovation Authority), and industry (e.g. Samsung, Foxconn, Intel, Refael, Ping-An). The first core-sets were developed for open mathematical problems during his P.hD in the University of Tel-Aviv under the supervision of Prof. Micha Sharir and Prof. Amos Fiat. Now his RBD Labs consist of > 20 graduate students. See lab’s web-site for more details: https://sites.hevra.haifa.ac.il/rbd/

  • CS Yearly Project Fair

    CS Yearly Project Fair

    Date:
    Tuesday, 26.6.2018, 16:30
    Place:
    CS Taub Lobby and 1st Floor

    CS Labs invited you to visit the Yearly Project Fair that will be held on Tuesday, 26, 2018, starting at 16:30, in the CS Taub Lobby and 1st Floor.

    More details in the attached poster.

    You are all invtied!

  • Metabolic Modeling for Bioengineering

    Speaker:
    Edward Vitkin, Ph.D. Thesis Seminar
    Date:
    Sunday, 1.7.2018, 14:30
    Place:
    Taub 601
    Advisor:
    Dr. Zohar Yakhini

    Efficient and sustainable conversion of biomass into valuable products is a major challenge for bioengineering. The composition of the feedstock biomass and the ability of microorganisms to efficiently ferment it are two most critical factors influencing the process efficiency. Intelligent design that addresses both these factors can greatly benefit from organism metabolic models and from using them in simulations and in computer-assisted optimization of the fermentation processes. In this talk we will cover several aspects of such simulations. We will discuss the construction and improvement of single organism metabolic models as well as present high-scale simulations to optimize multi-organism fermentation processes. Even in the two-organism fermentation system, many tested scenarios, such as reaction knockout analysis, may require solutions of millions of optimization tasks. We will present BioLEGO, a framework to support these heavy calculations, which is deployed as a Microsoft Azure Cloud service, leveraging the associated parallel computing capacities.