Colloquia and Seminars

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Upcoming Colloquia & Seminars

  • Pixel Club: Cached Compression of Packet Classifiers

    Janos Tapolcai & Gabor Retvari (Budapest University of Technology and Economics (BME)
    Wednesday, 8.7.2015, 11:30
    EE Meyer Building TBD

    Packet classification is a building block in many network services such as routing, filtering, intrusion detection, accounting, monitoring, load-balancing and policy enforcement. Compression has gained attention recently as a way to deal with the expected increase of classifiers size. Typically, compression schemes try to reduce a classifier size while keeping it semantically-equivalent to its original form. Inspired by the advantages of popular compression schemes (e.g. JPEG and MPEG), in the presentation I overview the applicability of lossy compression to create packet classifiers requiring less memory than optimal semantically-equivalent representations. Our objective is to find a limited-size classifier that can correctly classify a high portion of the traffic so that it can be implemented in commodity switches with classification modules of a given size. Next an optimal dynamic programming based algorithms for several versions of the problem is presented and described how to treat the small amount of traffic that cannot be classified, especially in software-defined networks. We evaluate their performance on real classifiers and traffic traces and show that in some cases we can reduce a classifier size by orders of magnitude while still classifying almost all the traffic correctly. The presentation is concluded with an outlook on more general applications of lossy compression.

    Janos Tapolcai received his M.Sc. (’00 in Technical Informatics), Ph.D. (’05 in Computer Science) degrees from Budapest University of Technology and Economics (BME), Budapest, and D.Sc. ('13 in Engineering Science) from Hungarian Academy of Sciences (MTA). Currently he is an Associate Professor at the High-Speed Networks Laboratory at the Department of Telecommunications and Media Informatics at BME. His research interests include applied mathematics, combinatorial optimization, optical networks and IP routing, addressing and survivability. He is an author of over 110 scientific publications, he is the recipient of the Google Faculty Award and Best Paper Award in ICC'06, in DRCN'11. He is a TPC member of leading conferences such as IEEE INFOCOM (2012 - 2014), and is a winner of MTA Momentum (Lendulet) Program.

    Gábor Rétvári received the M.Sc. and Ph.D. degrees in electrical engineering from the Budapest University of Technology and Economics (BME). He is now a Senior Research Fellow at the High Speed Networks Laboratory, BME. He has been passionate about the questions of routing scalability for a long time and he has done plenty of research in this field, using a diverse set of mathematical tools ranging from abstract algebra to computational geometry and, more recently, information-theory. He maintains numerous open source scientific tools written in Perl, C and Haskell.

  • Scenario Based Programming for Mobile Applications

    Anat Berkman, M.Sc. Thesis Seminar
    Tuesday, 14.7.2015, 13:30
    Taub 701
    Prof. E. Yahav & Prof. D. Harel

    We introduce a novel method for creating mobile applications, integrating the Android SDK into PlayGo, a scenario-based behavioral programming framework. The framework we implemented allows creating mobile applications simply by using a visual GUI editor, and then incrementally “playing in” scenarios that construct the application behavior. This allows the developer to focus on the application behavior and interface rather than the syntax and code.

  • 3rd TCE Summer School

    3rd TCE Summer School

    Sunday, 2.8.2015, 11:30
    Computer Engineering Center, Fishbach Building, Technion

    NetFPGA Summer Course 2015

    Speakers: Noa Zilberman & Yury Audzevich
    Host: Mark Silberstein

    NetFPGA is an open source platform enabling researchers and instructors to build high-speed hardware-accelerated networking systems. The NetFPGA is the de-factor experimental platform for line-rate implementations of network research and it has a family of boards, supporting from 1GE to 100GE. This course will provide an introduction to prototyping and using high bandwidth networking devices on the NetFPGA – SUME platform, and discuss considerations in architecture and design for high performance devices. During the course the students will design and implement a project.

    This course is focused on the NetFPGA-SUME platform. Attendees will utilize a Linux-based PC equipped with NetFPGA hardware. Basic understanding of Ethernet switching and network routing is expected. Past experience with Verilog is useful but not required.

    The course is intended for students and  researchers interested in developing new hardware-accelerated network applications.

    The course attendance is free, but requires registration. Register here.

    For more information click here.

    Note that the Technion students who take the course for academic credit will get priority in accessing NetFPGA hardware.

    Short bio of our Tutors:

    Noa Zilberman
    is a Research Associate at the University of Cambridge Computer Laboratory in England. Zilberman has over 15 years of industrial experience in the telecommunication and semiconductor industries. In her last role, Zilberman was a senior principal chip architect in Broadcom’s Network Switching group. Her research interests include open-source research using the NetFPGA platform, switching architectures, high speed interfaces, network measurements and Internet topology. Zilberman is a Senior Member of IEEE, a member of ACM and Usenix, and has a PhD in Electrical Engineering from Tel Aviv University.

    Yury Audzevich is a Research Associate at the University of Cambridge Computer Laboratory in England. He is an expert on energy-efficient designs for high-bandwidth networking devices, and was the lead researcher of CONTEST (CONfigurable Transceiver Energy uSage Toolkit). Previously, he was an Alcatel-Lucent Research Associate at the University of Trento. His current research interests lie in the field of reconfigurable systems, circuit design and energy-efficiency aspects in communication architectures. Audzevich obtained his PhD in Information and Telecommunication technologies from the University of Trento.