Colloquia and Seminars

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Upcoming Colloquia & Seminars

  • CGGC Seminar: Shape Spaces of Polyhedral Meshes

    Speaker:
    Amir Vaxman (Vienna University of Technology, Austria)
    Date:
    Sunday, 26.5.2013, 12:00
    Place:
    Room 337-8 Taub Bld.

    Polyhedral meshes are meshes in which all faces are planar. These meshes are of paramount importance to architectural and industrial geometry, as such faces can be assumed with ease with plates of glass or wood. Furthermore, polyhedral meshes are considered as a discrete counterpart of continuous conjugate-parametrized surfaces. I will talk about methods to design such meshes by generalizing known methods from triangular-mesh processing, such as subdivision and deformation, and means to explore the shape spaces of such meshes with a given topology.

  • TCE Talk Series - Talk III: Computer Architecture

    Speaker:
    Prof. Alexandru Iosup (Delft University of Technology)
    Date:
    Monday, 27.5.2013, 10:00
    Place:
    Room 337-8 Taub Bld.

    This series of talks focuses on the research and education conducted by the PDS group in recent years, on topics such as grid and cloud computing, systems for massively multiplayer online games, big data, and gamification of higher education.

    Our research focuses on the modeling, the design, the implementation, and the analysis of parallel and distributed systems and algorithms. Our research is fundamental in that we aim to develop and evaluate generic methods and techniques, and application-driven in that the research is motivated by application areas. Most of our research is experimental: we try to build prototypes of systems, preferably used in the real world, to demonstrate the quality of the proposed solutions. Our education focuses on the design and delivery of higher education units, such as B.Sc. and M.Sc.-level courses, and on the design of novel teaching techniques for a new, multi-cultural generation of students. We validate our teaching techniques experimentally, by gradually deploying them in the classroom.

    The research part of our talks focuses on:
    - New approaches for performance evaluation and benchmarking of IaaS clouds, in the lecture "IaaS Cloud Benchmarking: Approaches, Challenges, and Experience"
    - Building distributed systems to support online games with massive player counts, in the lecture "Massivizing Social Games: Distributed Computing Challenges and High Quality Time"
    - Exploring scheduling in IaaS clouds, in the lecture "Scheduling in IaaS Cloud Computing Environments: Anything New?"
    - An empirical exploration of big data processing, in the lecture "A TU Delft Perspective on Big Data: Machine-Level Graph Processing and Time-Based Data Analytics"
    The education part of our talks focuses on:
    - Gamification as a technique for higher education, in the lecture "Gamification: Playful Teaching for Generation-X/-Y/-Z/…"

    Bio
    Alexandru Iosup is currently an Assistant Professor with the Parallel and Distributed Systems Group at TU Delft. He has received in 2009 his Ph.D. in Computer Science from the Delft University of Technology (TU Delft), the Netherlands. He was a visiting scholar at U. Wisconsin-Madison, U. Innsbruck, and U. California-Berkeley in the summers of 2006, 2008, and 2010, respectively. In 2011, Dr. Iosup has received a Veni grant (the Dutch equivalent of the US NSF CAREER.) He is the author of over 50 refereed scientific publications and have received several awards and distinctions, including best paper awards at IEEE CCGrid 2010, Euro-Par 2009, and IEEE P2P 2006. He has co-founded the Grid Workloads Archive; and the Peer-to-Peer, the Game, and the Failure Trace Archives, all of which provide open access to workload and resource operation traces from large-scale distributed computing environments. His long-term research interests are in the area of distributed computing systems and their applications (keywords: cloud computing, grid computing, peer-to-peer systems, scientific computing, massively multiplayer online games, scheduling, scalability, reliability, performance evaluation, workload characterization).

    The lectures will be given in English.

  • Haifux Club: Resource Management in Linux

    Speaker:
    Rami Rosen
    Date:
    Monday, 27.5.2013, 18:30
    Place:
    Taub 6
    Link:
    http://haifux.org/

    1. Resource management in Linux
    2. Kernel Namespaces implementation (kernel 3.8)
    3. Kernel Namespaces as an infrastructure for process virtualizaton

       - Network namespaces and pid namespaces kernel implementation
       - System calls for namespaces
       - usage examples - creating linux namespaces in user space and attaching process to these namespaces

    4. cgroup kernel implementation

       - cgroup VFS
       - cgroup filesystem ops for handling cgroups (create/attach processes, cgroup subsystem VFS specific operations, etc) examples
       - The cgroup release agent and the notification API + examples
       - Memory controller (memcg) example (disabling oom killer)
       - Two networking controllers examples
       - linbvgroup-tools + examples

    5. Checkpoint/Restart in brief

  • Pixel Club: On SIFT and their Scales

    Speaker:
    Viki Mayzels (EE, Technion)
    Date:
    Wednesday, 29.5.2013, 11:30
    Place:
    EE Meyer Building 1061

    Scale invariant feature detectors often find stable scales in only a few image pixels. Consequently, methods for feature matching typically choose one of two extreme options: matching a sparse set of scale invariant features, or dense matching using arbitrary scales. In this thesis we turn our attention to the overwhelming majority of pixels, those where stable scales are not found by standard techniques. We ask, is scale-selection necessary for these pixels, when dense, scale-invariant matching is required and if so, how can it be achieved? We make the following contributions: (i) We show that features computed over different scales, even in low-contrast areas, can be different; selecting a single scale, arbitrarily or otherwise, may lead to poor matches when the images have different scales. (ii) We show that representing each pixel as a set of SIFTs, extracted at multiple scales, allows for far better matches than single-scale descriptors, but at a computational price. Finally, (iii) we demonstrate that each such set may be accurately represented by a low-dimensional, linear subspace. A subspace to-point mapping may further be used to produce a novel descriptor representation, the Scale-Less SIFT (SLS), as an alternative to single-scale descriptors. These claims are verified by quantitative and qualitative tests, demonstrating significant improvements over existing methods.

  • Robust Epipolar Geometry Estimation using Noisy Pose Priors

    Speaker:
    Yehonatan Goldman, M.Sc. Thesis Seminar
    Date:
    Wednesday, 29.5.2013, 14:30
    Place:
    Taub 601
    Advisor:
    Prof. Ehud Rivlin and Prof. Ilan Shimshoni

    Epipolar geometry estimation is fundamental to many computer vision algorithms. It has therefore attracted a lot of interest in recent years, yielding high quality estimation algorithms for wide baseline image pairs. Currently many types of cameras (e.g., in smartphones and robot navigation systems) produce geo-tagged images containing pose and internal calibration data. Exploiting this information as part of an epipolar geometry estimation algorithm may be useful but not trivial, since the pose measurement may be quite noisy. We introduce SOREPP, a novel estimation algorithm designed to exploit pose priors naturally. It sparsely samples the pose space around the measured pose and for a few promising candidates applies a robust optimization procedure. It uses all the putative correspondences simultaneously, even though many of them are outliers, yielding a very efficient algorithm whose runtime is independent of the inlier fractions. SOREPP was extensively tested on synthetic data and on hundreds of real image pairs taken by a smartphone. Its ability to handle challenging scenarios with extremely low inlier fractions of less than 10% was demonstrated as was its ability to handle close cameras. It outperforms current state-of-the-art algorithms that do not use pose priors as well as other algorithms that do.

  • ceClub: Spinal Codes

    Speaker:
    Jonathan Perry (MIT)
    Date:
    Wednesday, 5.6.2013, 11:30
    Place:
    Room 337-8 Taub Bld.

    Handling noise and interference in wireless networks requires adaptive, high-performance error correction. Spinal codes are a new rateless error correcting code that iteratively applies a hash function to message bits, ensuring that two input messages that differ in even one bit produce very different coded sequences after the point at which they differ. Spinal codes offer a flexible tradeoff between computational cost and performance. Because spinal codes are rateless, they automatically adapt to changing channel conditions.

    The resulting system achieves better throughput than LDPC and Raptor codes, and despite the large state space induced by the hash output, the message can be recovered efficiently; a preliminary hardware prototype decodes at 10Mbps.

    No prior knowledge of coding theory is required.

    More information at http://nms.csail.mit.edu/spinal/

    Bio:
    Jonathan Perry received a B.Sc in CS from Tel-Aviv University in 2003. Jonathan worked in high performance computing and in distributed systems until 2010, when he joined MIT's Ph.D. program. Co-advised by Hari Balakrishnan and Devavrat Shah, Jonathan is currently working on error correcting codes and efficient network transport.

  • Theory Seminar: TBA

    Speaker:
    Michael Dinitz (Weizmann Institute of Science)
    Date:
    Wednesday, 5.6.2013, 12:30
    Place:
    Taub 201

    TBA

  • Cost Aware Fault Recovery in Clouds

    Speaker:
    Assaf Israel, M.Sc. Thesis Seminar
    Date:
    Wednesday, 5.6.2013, 15:30
    Place:
    Taub 601
    Advisor:
    Prof. Danny Raz

    Maintaining high availability of Ifrastructure-as-a-Service services at a reasonable cost is a challenging task that received recent attention due to the growing popularity of Cloud computing as a preferred means of affordable IT outsourcing. In large data-centers, faults are prone to happen and thus the only reasonable cost-effective method of providing high availability of services is an SLA aware recovery plan; that is, a mapping of the service VMs onto backup machines where they can be executed in case of a failure. The recovery process may benefit from powering on some of these machines in advance, since redeployment on powered machines is much faster. However, this comes with an additional maintenance cost, so the real problem is how to balance between the expected recovery time improvement and the cost of machines activation. We model this problem as an offline optimization problem and present a bicriteria approximation algorithm for it. While this is the first performance guaranteed algorithm for this problem, it is somewhat complex to implement in practice. Thus, we further present a much simpler and practical heuristic based on a greedy approach. We evaluate the performance of this heuristic over real data-center data, and show that it performs well in terms of scale, hierarchical faults and variant costs. Our results indicate that our scheme can reduce the overall recovery costs by 10-15% when compared to currently used approaches. We also show that fault recovery cost aware VM placement may farther help reducing the expected recovery costs, as it can reduce the backup machine activations costs.

  • TCE Talk Series - Talk IV: Computer Architecture

    Speaker:
    Prof. Alexandru Iosup (Delft University of Technology)
    Date:
    Thursday, 6.6.2013, 10:00
    Place:
    Room 337-8 Taub Bld.

    This series of talks focuses on the research and education conducted by the PDS group in recent years, on topics such as grid and cloud computing, systems for massively multiplayer online games, big data, and gamification of higher education.

    Our research focuses on the modeling, the design, the implementation, and the analysis of parallel and distributed systems and algorithms. Our research is fundamental in that we aim to develop and evaluate generic methods and techniques, and application-driven in that the research is motivated by application areas. Most of our research is experimental: we try to build prototypes of systems, preferably used in the real world, to demonstrate the quality of the proposed solutions. Our education focuses on the design and delivery of higher education units, such as B.Sc. and M.Sc.-level courses, and on the design of novel teaching techniques for a new, multi-cultural generation of students. We validate our teaching techniques experimentally, by gradually deploying them in the classroom.

    The research part of our talks focuses on:
    - New approaches for performance evaluation and benchmarking of IaaS clouds, in the lecture "IaaS Cloud Benchmarking: Approaches, Challenges, and Experience"
    - Building distributed systems to support online games with massive player counts, in the lecture "Massivizing Social Games: Distributed Computing Challenges and High Quality Time"
    - Exploring scheduling in IaaS clouds, in the lecture "Scheduling in IaaS Cloud Computing Environments: Anything New?"
    - An empirical exploration of big data processing, in the lecture "A TU Delft Perspective on Big Data: Machine-Level Graph Processing and Time-Based Data Analytics"
    The education part of our talks focuses on:
    - Gamification as a technique for higher education, in the lecture "Gamification: Playful Teaching for Generation-X/-Y/-Z/…"

    Bio
    Alexandru Iosup is currently an Assistant Professor with the Parallel and Distributed Systems Group at TU Delft. He has received in 2009 his Ph.D. in Computer Science from the Delft University of Technology (TU Delft), the Netherlands. He was a visiting scholar at U. Wisconsin-Madison, U. Innsbruck, and U. California-Berkeley in the summers of 2006, 2008, and 2010, respectively. In 2011, Dr. Iosup has received a Veni grant (the Dutch equivalent of the US NSF CAREER.) He is the author of over 50 refereed scientific publications and have received several awards and distinctions, including best paper awards at IEEE CCGrid 2010, Euro-Par 2009, and IEEE P2P 2006. He has co-founded the Grid Workloads Archive; and the Peer-to-Peer, the Game, and the Failure Trace Archives, all of which provide open access to workload and resource operation traces from large-scale distributed computing environments. His long-term research interests are in the area of distributed computing systems and their applications (keywords: cloud computing, grid computing, peer-to-peer systems, scientific computing, massively multiplayer online games, scheduling, scalability, reliability, performance evaluation, workload characterization).

    The lectures will be given in English.

  • TCE Talk Series - Talk I: Computer Architecture (4 hours)

    Speaker:
    Henry Taub Distinguished Visitor Prof. Yale Patt (The University of Texas at Austin)
    Date:
    Thursday, 13.6.2013, 14:30
    Place:
    EE Meyer Building 165

    Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

    Course Details:


    Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

    Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

    Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

    Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

    Bio:
    Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

    The lectures will be given in English.

    Academic credit for registered students (exam required).

    The next talks in this series will be held as following:
    Talk II: Friday, June 14th, 09:00 (3 hours)
    Talk III: Thursday, June 20th, 14:30 (4 hours)
    Talk IV: Friday, June 21st, 09:00 (3 hours)

  • TCE Talk Series - Talk II: Computer Architecture (3 hours)

    Speaker:
    Henry Taub Distinguished Visitor Prof. Yale Patt (The University of Texas at Austin)
    Date:
    Friday, 14.6.2013, 09:00
    Place:
    EE Meyer Building 165

    Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

    Course Details:

    Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

    Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

    Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

    Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

    Bio:
    Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

    The lectures will be given in English

    Academic credit for registered students (exam required).

    The next talks in this series will be held as following:
    Talk III: Thursday, June 20th, 14:30 (4 hours)
    Talk IV: Friday, June 21st, 09:00 (3 hours) .

  • TCE Talk Series - Talk III: Computer Architecture (4 hours)

    Speaker:
    Henry Taub Distinguished Visitor Prof. Yale Patt (The University of Texas at Austin)
    Date:
    Thursday, 20.6.2013, 14:30
    Place:
    EE Meyer Building 165

    Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

    Course Details:

    Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

    Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

    Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

    Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

    Bio:
    Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

    The lectures will be given in English

    Academic credit for registered students (exam required).

    The next talks in this series will be held as following:
    Talk IV: Friday, June 21st, 09:00 (3 hours)

  • TCE Talk Series - Talk IV: Computer Architecture (3 hours)

    Speaker:
    Henry Taub Distinguished Visitor Prof. Yale Patt (The University of Texas at Austin)
    Date:
    Friday, 21.6.2013, 09:00
    Place:
    EE Meyer Building 165

    Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

    Course Details:

    Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

    Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

    Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

    Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

    Bio:
    Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

    The lectures will be given in English

    Academic credit for registered students (exam required).