Amit Berman (EE. Technion)
Wednesday, 8.5.2013, 11:30
The invention of semiconductor technology has marked a new era in memory devices: SRAM, DRAM, Flash and more. The ever-increasing rate of data production and consumption stimulates the development of high-performance memory devices. At times, high-density scaling drives new applications and ways of operation. However, device advancement presents trade-offs and ever growing challenges. High-performance memory (SRAM, DRAM) suffers from relatively low density, higher power consumption and, most important, data volatility. Similarly, high-density, non-volatile memory (Flash) exhibits relatively low performance. As device technology shrinks, massive inter-cell interference is limiting the achievable density, high variations among memory cells result in degraded read/write performance, and endurance is limited due to cell degradation. Over the past decade, the various challenges have been the subject of much research, mostly focused on technology- and circuit-level innovation. Other challenges (e.g. restricted overwrite due to one-way charge level changes) were addressed by coding techniques.
In our research, we explore cross-layer methods for enhancing memory characteristics (density, read/write performance, power and reliability). Specifically, inter-cell interference is mitigated by using constrained coding to prevent the data patterns that cause interference beyond a predefined limit; read performance is improved by way of a speculative early sensing mechanism, whereby cell read time is dynamically minimized through premature sensing along with guaranteed error detection; multi-level cell write speed is improved by minimal maximum-level programming, whereby cells are being written gradually, different same-size pages are stored in different numbers of cells, and bit fractions of any given page are stored in a cell; and the number of possible rewrites between block erasures is increased via page management that permits writing to retired pages when proper data is available. Our schemes are presented and evaluated mostly in the context of NAND Flash, with several extensions to DRAM and SRAM, but some are also applicable to emerging memory technologies such as PCM.
Ph.D. Seminar. Advisor: Prof. Yitzhak Birk.
Bio: Amit Berman is a Ph.D candidate at the Electrical Engineering Department, Technion - Israel Institute of Technology. He received the B.Sc and M.Sc in Electrical Engineering at 2006 and 2010 respectively. He is a recipient of several awards, including Hershel Rich Technion Innovation award, Intel research award, and HPI fellowship. He held engineering and management positions at Intel and Saifun (acquired by Spansion) during 2003-2009. He authored several international publications in the field of non-volatile memory and computer architecture and holds several pending US patents.