CGGC Seminar: Solid Modelling for VLSI Design

Speaker:
Elisha Sacks (Computer Science, Purdue University)
Date:
Monday, 7.9.2015, 13:00
Place:
Taub 401

Solid modelling is a core technology in VLSI process and device modelling.

Intel has found that commercial software can be unreliable and slow. An important example is computing an offset of a polyhedron. Prior work on robust computational geometry makes assumptions that conflict with the application requirements, notably the need to perform finite-element analysis on solid models. I will describe preliminary work on a robustness technique that meets these requirements. I will present a novel approximate offset algorithm that I have implemented using this robustness technique. I will conclude with a discussion of the outstanding problem of eliminating small features from polyhedral meshes.

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