Examples    For    Veritech   

 

We used a group of well-known problems to demonstrate the strength of the tool we built. You can see the examples sorted by translation (ex. CORE to SMV) or sorted by example (to see how various tools handle the same problem).

We are working on a new design for the example page. Meanwhile, examples for new translation are added only to the "sort by translation" section as a zip file that contain all the examples. You can look at our new site for easiest navigation through the examples. Please notice that the new site do not contain yet all the examples that we have.

 


Choose By Translation
Language from CDL to CDL

Lotos

get examples zip file

Murphi

click here

 

PetriNet

see project documentation

see project documentation

SAL

get examples zip file get examples zip file

SMV

click here click here

Spin

click here get examples zip file

STeP

click here get examples zip file

Translation from specification language A to specification language B, where neither A nor B is the core specification language, is done via the core language (that is A to core to B).  To demonstrate this we created translation from SMV to: Murphi, Spin snd Step.







Choose By Example

Alternating Bit Protocol
Binary Counter Mod 8
Bounded Buffer
Dining Philosophers
Inverter
Leader's Election
Mutex
Mutual Exclusion
Nondeterministic Parallel Buffers
Open Safe
Request Handler
Semaphore
Simple Buffer
Sliding Windows







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