Prof.Emeritus Michael Yoeli
Publications on Asynchronous Networks
A. Self-Timed Double-Rail Systems
[DGY89a] David I., Ginosar R. and Yoeli M., ``An Efficient
Implementation of Boolean Functions and Finite State Machines as
Self-Timed Circuits'', Computer Architecture News (CAN), pp. 91-
104, Dec. 89.
[DGY89b] David I., Ginosar R. and Yoeli M., ``Self-Timed
Architecture of a Reduced Instruction Set Computer'' Technical
Report No. 732, Dept. Elect. Eng., Technion, Nov. 1989.
[DGY90] I. David, R. Ginosar and M. Yoeli, `` Self-Timed is
Self-Diagnostic'', Technical Report No. 758, Dept. Elect. Eng.,
Technion, Nov. 1990.
[DGY92a] I. David, R. Ginosar and M. Yoeli, ``An Efficient
Implementation of Boolean Functions as Self-Timed Circuits,''
IEEE Transactions on Computers, Jan. 1992, pp. 2-11.
[DGY92b] I. David, R. Ginosar and M. Yoeli, ``Implementing
Sequential Machines as Self-Timed Circuits,'' IEEE Transactions
on Computers, Jan. 1992, pp. 12-17.
B. Asynchronous Networks
[YK2000] M.YOELI and E. KOHN, Petrify-Based Verification of
Asynchronous Circuits - Three Case Studies, Technical Report
CS-2000-02, Dept. of Computer Science, Technion, Haifa.
http://www.cs.technion.ac.il/users/wwwb/cgi-bin/tr-get.cgi/2000/CS/CS-2000-02.ps
[Yoe98a] M.YOELI, Modulo-3 Transition Counter: A Case Study in
LOTOS-Based Verification, Technical Report CS0950, Dept. of
Computer Science, Technion, Haifa.
http://www.cs.technion.ac.il/users/wwwb/cgi-bin/tr-get.cgi/1998/CS/CS0950.ps
[YG98] M.YOELI and A.GINZBURG, LOTOS-based Verification of
Asynchronous Circuits, Technical Report CS0951, Dept. of Computer
Science, Technion, Haifa.
http://www.cs.technion.ac.il/users/wwwb/cgi-bin/tr-get.cgi/1998/CS/CS0951.ps
[YG98a] M.YOELI and A.GINZBURG, Petri-net Based Verification of
Asynchronous Circuits, Technical Report CS0959, Dept. of Computer
Science, Technion, Haifa.
http://www.cs.technion.ac.il/users/wwwb/cgi-bin/tr-get.cgi/1999/CS/CS0959.ps
[BSY92b] H.BELHADJ, G.SAUCIER and M.YOELI, From Trace Graphs to
Modular Delay-Insensitive Circuits", 26th Hawaii International
Information Systems Conference, 6-8 January 1993, Hawaii.
[BSY92c]H.BELHADJ, G.SAUCIER and M.YOELI, Asynchronous VLSI
Circuits Synthesis : The State of the Art, EDAC-EUROASIC'93.
[SY92] N.SHINTEL and M.YOELI, Synthesis of Modular Networks from
Petri-Net Specifications, Technical Report #743, Dept. of
Computer Science, Technion, Haifa, 1992.
[Yo91] M.YOELI, Formal Verification of Modular Networks Based on
Dynamic Behavior, Technical Memo, Dept. of Computer Science,
Technion, Haifa, 1991.
[GY91] A.GINZBURG and M.YOELI, Synthesis of Delay-Insensitive
Circuits Specified by Trace Graphs, Technical Report #663, Dept.
of Computer Science, Technion, Haifa, 1991.
[Yo90] M.YOELI, Net-Based Synthesis of Delay-Insensitive
Circuits, Technical Report #609, Dept. of Computer Science,
Technion, Haifa, 1990.
[RY88] I.REICHER and M.YOELI, Net-Based Modeling of Communicating
Parallel Processes with Applications to VLSI Design, Technical
Report #532, Dept. of Comp. Science, Technion, Haifa, 1988.
[Yo87a] M.YOELI, "Structured Design of the Control Parts of
Self-Timed VLSI Systems", Proc. Second International Conference
on Computers and Applications, Beijing, June 1987, pp.839 - 841.
[Yo87b] M.YOELI, "Specification and Verification of Asynchronous
Circuits Using Marked Graphs", in: Concurrency and Nets, Advances
in Petri Nets, Springer-Verlag, 1987, pp.605-622.
[YG80] M.YOELI and A.GINZBURG, "Control Nets for Parallel
Processing", Proc. 8th World IFIP Congress 80, Tokyo and
Melbourne, North-Holland Publ. Comp., 1980, pp.71 - 76.
[BY79] J.BRZOZOWSKI and M.YOELI, "On a Ternary Model of Gate
Networks", IEEE Trans. Comp., March 1979, pp.178 - 184.
[BY76] J.BRZOZOWSKI and M.YOELI, Digital Networks, Prentice- Hall
Publ., 1976.