Abstract:

I'll present a joint work with Prof. Rajeev Alur on modular design of
resource scheduling in embedded control systems. Specifically, we
propose omega-regular languages as an interface for resource sharing
in embedded systems. For example, imagine two software components that
share some resource (e.g. CPU). We propose that each component
specifies an omega regular language over the alphabet {0,1} of safe
schedules, i.e., if w=w(1),w(2),... is in this languages, and the
component gets the resource in every time slot t for which w(t)=1,
then the component meets its performance requirements. The main
advantage of this interface is that it allows modular analysis of each
component and then the constraints can be combined to a schedule that
is good for all the components using languages intersection (and
renaming). We will discuss applications of this idea for
time-triggered architectures and with Logical Execution Time (LET).

I'll present theoretical results concerning applications of the above
approach to control systems (where controllers are implemented by a
software that share resources) and a tool called RTComposer that
allows compositional analysis of components in Real-Time Java.
Scheduling specifications can be given as periodic tasks, or using
temporal logic, or as omega-automata . Components can be added
dynamically, and non-real-time components are allowed. The benefits of
the approach will be demonstrated using case studies.