Abstract:

The Merrimac streaming supercomputer project aims to develop a
scientific computer that offers an order of magnitude or more
improvement in performance per unit cost, unit power, and unit
floor-space compared to cluster-based scientific computers built from
the same underlying semiconductor and packaging technology. Merrimac's
high efficiency arises from the stream architecture of the processing
node and the advanced high-radix interconnection network used for
communication between the nodes. The stream architecture matches the
capabilities of modern semiconductor technology, which allows us to
place hundreds of functional units on a single chip but provides
limited global on-chip and off-chip bandwidths, with compute-intensive
parallel applications. Organizing the computation into streams and
exploiting the resulting locality using a register hierarchy enables a
stream architecture to reduce the memory bandwidth required by
representative computations by an order of magnitude or more.  Hence a
processing node with a fixed memory bandwidth (which is expensive) can
support an order of magnitude more arithmetic units (which are
inexpensive).  Because each node has much greater performance (128
GFLOPs in our current design) than a conventional microprocessor, a
streaming supercomputer can achieve a given level of performance with
fewer nodes, reducing costs, simplifying system management, and
increasing reliability. In this talk I will present the technology
trends leading to Merrimac's design, and sketch the design of the
Merrimac streaming scientific computer, which stresses efficiency,
scalability, and fault tolerance. I will also discuss some key
characteristics of Merrimac that make it a good target for aggressive
compiler optimizations. A key part of my work although deals with
analysis and mapping of scientific algorithms and applications onto
Merrimac, and demonstrate the architecture's effectiveness through a
molecular dynamics application and finite element method code case
studies.


Bio:

Mattan Erez received a B.Sc. in Electrical Engineering and a B.A. in
Physics from the Technion, Israel Institute of Technology in 1999. He
subsequently received his M.S in Electrical Engineering from Stanford
University in 2002. His previous work experience includes army service
at a technical research branch of the Israeli Defense Force, and
working as a computer architect in the Israeli Processor Architecture
Research team, Intel Corporation. As a Ph.D. candidate at Stanford
University he participated in the Smart Memories project and is
currently the leader of the Merrimac Stanford Streaming Supercomputer
project, where his main areas of interest are architecture and its
interaction with the compilation system and the programmer.