Technical Report MSC-2015-02

Title: Enhancing Energy-Performance for Power Constrained SoC Systems
Authors: Rami Jioussy
Supervisors: Avi Mendelson
PDFCurrently accessibly only within the Technion network
Abstract: System on Chip (SoC) based heterogeneous architectures are becoming the de facto standard of low-end systems. Hence, optimal power management for these platforms is a highly important goal. Prior research works have suggested approaches and techniques to schedule computation for parallel execution on the different compute devices (hence hybrid execution), with the goal of improving performance, while only a few focused on energy-performance. All those research works have been targeted at hybrid platforms with CPU and discrete GPUs, for which performance or energy can be optimized independently per device. Those approaches suggest that optimizing energy-performance for hybrid execution is achieved by different schemes for work partitioning (for example, using OpenCL kernels), followed by runtime power management (for example, OS balanced-mode power policy). In the SoC environment, optimizing both energy and performance cannot be addressed directly with these prior techniques. They either become inapplicable or their proposed solution will be suboptimal. This research presents a novel approach; it suggests an offline method which learns the program behavior (performance, energy) on each of the platform devices, to determine both optimal work partitioning as well as device frequencies, in order to maximize energy-performance during hybrid execution. Our proposed approach demonstrates 23% average improvement in energy-performance for a set of OpenCL workloads running on an off-the-shelf SoC platform, compared to an OS balanced-mode power policy.
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