Technical Report CS0763

TR#:CS0763
Class:CS
Title: A REAL-TIME SYSTOLIC INTEGER MULTIPLIER (Extended Abstract).
Authors: G. Even
PDFCS0763.pdf
Abstract:

We describe the construction of two practical real-time systolic bit-serial multipliers: a pipelined multiplier and a non-pipelined multiplier. Out non-pipelined multiplier requires roughly half the hardware (number of full-adders) as compared to Atrubin's multiplier, which is the best real-time systolic multiplier known to date. Our starting point is a serial/parallel multiplier which is not systolic, has a large number of primary inputs and does not support pipeling. We modify this design step by step using systematic methodologies until our design is obtained. The methodologies used in this design are: broadcast elimination, replacing parallel inputs with a broadcast mechanism and adding a simplified version of the circuit in order to enable pipeling. Applying these methodologies yields an improved circuit the correctness of which is easily understood.

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