Technical Report CS0609

Authors: Michael Yoeli
Abstract: This paper is an introduction to a novel fonnal theory of delay-insensitive circuits, their verification and synthesis. We co.nsider asynchronous circuits, obtained by suitably interconnecting basic components ("modules"). Such a circuit is "delay-insensitive" if its correct behavior is independent of the delays of its modules and its connecting wires. The novel features of our approach are,the following: (1) We develop a suitable fonnal delay and race model of modular circuits; (2) We define in a new way the concept "implementation satisfies specification"; (3) We use (a suitable algebraic representation of) Petri nets for both the high-levelı specification as well as the synthesis of delay-insensitive circuits. Our synthesis methodı is "direct", i e. we do not need to transfonn the given specification net into a finite-stateı machine. The synthesis method derived in this paper is restricted to certain classes of Petri nets.ı However, research is in progress to expand the applicability of our design approach.
CopyrightThe above paper is copyright by the Technion, Author(s), or others. Please contact the author(s) for more information

Remark: Any link to this technical report should be to this page (, rather than to the URL of the PDF files directly. The latter URLs may change without notice.

To the list of the CS technical reports of 1990
To the main CS technical reports page

Computer science department, Technion