|Title:||Synthesis of Delay-Insensitive Circuits Based on Marked Graphs
|Authors:||M. Yoeli and I. Reicher
|Abstract:||This paper develops a methodology for the synthesis of modular, correct-by-contruction, delay-insensitive Circuits. It introduces a novel theory of modular, asynchronous circuits and uses labeled marked graphs for both the high-level specificatibn as well as the synthests of delay-intensitive circuits. The present paper is restricted to the use of (Huller's) C-elements, inverters, anq wires as basic modules. However, research is in progress with the purpose of extending the set of basic modules.|
|Copyright||The above paper is copyright by the Technion, Author(s), or others. Please contact the author(s) for more information|
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