|Title:||Riddle: A Foundation for Test Generation on a High Level Design Description
|Authors:||G.M. Silberman and I. Spillinger
|Abstract:||We present a formal approach to the analysis of a VLSI design described at the high level, which produces information conducive to the acceleration cf test generation algorithms. This analysis yields as its main product, information which can be used to reduce the amount of effort expended during backtracing, by guiding this process towards decisions (assignments) less likely to cause conflicts, and mmimizing the amount of work between backtracks. RIDDLE, an algorithm which performs this analysis in time linear in the number of signals, is introduced. Expcrimenta1 results for the special case of combinatorial gate level designs are also given.|
|Copyright||The above paper is copyright by the Technion, Author(s), or others. Please contact the author(s) for more information|
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