|Title:||An O(log N) Parallel Connectivity Algorithm
|Authors:||Yossi Shiloach and Uzi Vishkin
|Abstract:||A parallel algorithm which uses O(n+m) processors to find the connected components of an undirected graph with n vertices and m edges in time O(log n) is presented. We assume that the processors have access to a common memory. Simultaneously access to the same memory location is allowed for both read and write instructions.|
|Copyright||The above paper is copyright by the Technion, Author(s), or others. Please contact the author(s) for more information|
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