תמונה של פרופ' מיכאל יואלי

פרופ' מיכאל יואלי ז"ל

דף זיכרון:
http://www.cs.technion.ac.il/he/people/memoriam/z--myoeli/
תחומי עניין במחקר
איפיון ואימות של מערכות-חומרה.
פרסומים נבחרים
DAVID, I., GINOSAR, R., and YOELI, M., "An efficient implementation of boolean functions as self-timed circuits", IEEE Transactions on Computers, pp. 2-11, 1992.
DAVID, I., GINOSAR, R., and YOELI, M., "Implementing Sequential Machines as Self-Timed Circuits,'' IEEE Transactions on Computers, pp. 12-17, 1992.
GINZBURG, A., and YOELI, M., "Synthesis of delay-insensitive circuits specified by trace graphs", TR, CS663, Department of Computer Science, Technion, Haifa, 1991.
YOELI, M., "Structured deSign of the control parts of self-timed VLSI systems", Proceeding of the Second International Conference on Computers and Applications, Beijing, pp.839-841, 1987.
BRZOZOWSKI, J., and YOELI, M., Digital Networks, Prentice-Hall, 1976.
YOELI, M., and ETZION, T., "Behavioral equivalence of concurrent systems", in Applications and Theory of Petri Nets, A. Pagnoni and G. Rozenberg, (eds.), Informatik-Fachberichte. Vol. 66, pp.292-305, Springer Verlag,1983.
ETZION, T., and YOELI, M., "Super-nets and their hierarchy", Theoretical Computer Science, pp.243-272, 1983.
PORAT, S., AND YOELI, M., "Towards a hierarchy of nets", Journal of Computer and Systems Sciences, pp.198-206, 1984.
Reicher, I., and Yoeli, M., "Net-based modeling of communicating parallel processes with applications to VLSI design", TR CS532, Department of Computer Science, Technion, 1988.
YOELI, M.,"Specification and verification of asynchronous circuits using marked graphs", in Concurrency and Nets, Advances in Petri Nets, K. Voss, H.J. Genrich, and G. Rozenberg (eds.), Springer Verlag, pp. 605-622, 1987.
SHINTEL, N., and YOELI, M., "Synthesis of modular networks from Petri-net specifications", TR CS743, Department of Computer Science, Technion, 1992.
WOLFSTAHL, Y., and YOELI, M., "An equivalence theorem for labeled marked graphs", Journal of Parallel and Distributed Computing, 1994, pp.886-891.
YOELI, M., and GINZBURG, A., Petri-net based verification of asynchronous circuits", TR CS0959, Department of Computer Science, Technion, 1999.
YOELI, M., "Examples of LOTOS-based verification of asynchronous circuits", TR CS-2001-08, Department of Computer Science, Technion, 2001.
YOELI, M., and GINZBURG, A., LOTOS/CADP-based verification of asynchronous circuits, TR CS-2001-09, Department of Computer Science, Technion, 2001.
YOELI, M., and ETROG, N., "Introduction to digital circuit verification", TR CS-2001-10, Department of Computer Science, Technion, 2001.
YOELI, M., "Decompositions of asynchronous circuits", TR CS-2001-16, Department of Computer Science, Technion, 2001.