# קולוקוויום וסמינרים

כדי להצטרף לרשימת תפוצה של קולוקוויום מדעי המחשב, אנא בקר בדף מנויים של הרשימה.

## קולוקוויום וסמינרים בקרוב

• ### ceClub: Secure Logical Isolation for Multi-tenancy in Cloud Storage

דובר:
הילל קולודנר (י.ב.מ.)
תאריך:
יום רביעי, 22.5.2013, 11:30
מקום:
טאוב (יפורסם)
קישור:
http://ceclub.technion.ac.il/

Storage cloud systems achieve economies of scale by serving multiple tenants from a shared pool of servers and disks. This leads to the commingling of data from different tenants on the same devices. Typically, a request is processed by an application running with sufficient privileges to access any tenant's data; this application authenticates the user and authorizes the request prior to carrying it out. Since the only protection is at the application level, a single vulnerability threatens the data of all tenants, and could lead to cross-tenant data leakage, making the cloud much less secure than dedicated physical resources.

To provide security close to physical isolation while allowing complete resource pooling, we propose Secure Logical Isolation for Multi-tenancy (SLIM). SLIM incorporates the first complete security model and set of principles for the safe logical isolation between tenant resources in a cloud storage system, as well as a set of mechanisms for implementing the model. These principles lead to the potentially costly conclusion that each request should be handled by a new process. We present a detailed design, implementation and performance analysis of a process factory to greatly reduce the cost while still preserving secure isolation. Finally, we show how to implement SLIM for OpenStack Swift and present performance results, showing SLIM with our optimizations provides an order of magnitude improvement over a naive implementation of process isolation.

Authors: Michael Factor, David Hadas, Aner Hamama, Nadav Har'el, Hillel Kolodner, Anil Kurmus, Eran Rom, Alexandra Shulman-Peleg and Alessandro Sorniotti.

Bio:
Hillel Kolodner is a Senior Technical Staff Member in the Systems Technologies department at the IBM Haifa Research Lab. In the past he has worked on the implementation of Java for multiprocessor servers, especially on automatic memory management (garbage collection). Recently, he has worked on virtualization and management technologies for cloud computing. Currently, he is working on cloud object stores and is the PI for VISION Cloud , an European Commission FP7 Integrated Project developing storage cloud technologies. Hillel holds a Ph.D. and M.S. in Computer Science from the Massachusetts Institute of Technology, and a B.A. in Mathematics and a B.S.E. in Computer Science from the University of Pennsylvania.

• ### Efficient Query Recommendation

דובר:
גרגורי בורודין, הרצאה סמינריונית למגיסטר
תאריך:
יום רביעי, 22.5.2013, 12:30
מקום:
טאוב 601
מנחה:
Prof. Yaron Kanza

In large organizations, frequently the database has a large and intricate schema, hence, formulating queries is cumbersome. In such organizations, users can benefit from finding relevant queries in the query log of the database -- queries that can serve as an initial example for query formulation, or queries that were written by experts and elucidate how to write the query in an optimized manner. In this work we describe a recommendation system that assists users by providing a query search capability over a repository of SQL queries. We distinguish between two types of search -- semantic search and syntactic search. In semantic search, queries are deemed similar if they were written for the same task. In syntactic search, queries are considered similar if they look similar to an ordinary user. We will illustrate these two types of similarity and the differences between them. We will present different methods to test similarity among queries, and experimental results that illustrate the effectiveness of our methods. Finally, we will demonstrate a recommendation system that assists users finding queries under each one of the two search semantics.

• ### Theory Seminar: From Hierarchical Partitions to Hierarchical Covers: Optimal Fault-Tolerant Spanners for Doubling Metrics

דובר:
שי סולומון (מכון ויצמן למדע)
תאריך:
יום רביעי, 22.5.2013, 12:30
מקום:
טאוב 201
קישור:

A {\em $(1+\eps)$-spanner} for a doubling metric $(X,\delta)$ is a subgraph $H$ of the complete graph corresponding to $(X,\delta)$, which preserves all pairwise distances to within a factor of $1+\eps$. A natural requirement from a spanner is to be robust against node failures, so that even when some of the nodes in the network fail, the remaining part would still provide a $(1+\eps)$-spanner. The spanner $H$ is called a {\em $k$-fault-tolerant $(1+\eps)$-spanner}, for any $0 \le k \le n-2$, if for any subset $F \subseteq X$ with $|F| \le k$, the graph $H \setminus F$ (obtained by removing from $H$ the vertices of $F$ and their incident edges) is a $(1+\eps)$-spanner for $X \setminus F$.

In this talk I will show how to obtain an optimal construction of fault-tolerant spanners for doubling metrics. Specifically, for any $n$-point doubling metric, any $\eps > 0$, and any integer $0 \le k \le n-2$, our construction provides a $k$-fault-tolerant $(1+\eps)$-spanner with optimal degree $O(k)$ within optimal time $O(n \log n + k n)$. We then strengthen this result to provide near-optimal (up to a factor of $\log k$) guarantees on the diameter and weight of our spanners.

Our result settles several fundamental open questions in this area, culminating a long line of research that started with the STOC'95 paper of Arya et al. and the STOC'98 paper of Levcopoulos et al. On the way to this result we develop a new technique for constructing spanners in doubling metrics. In particular, our spanner construction is based on a novel {\em hierarchical cover} of the metric, whereas most previous constructions of spanners for doubling and Euclidean metrics (such as the net-tree spanner) are based on {\em hierarchical partitions} of the metric.

The talk will be self-contained. During the talk I will present some open problems in this area.

• ### CGGC Seminar: Shape Spaces of Polyhedral Meshes

דובר:
אמיר וקסמן (אונ' וינה)
תאריך:
יום ראשון, 26.5.2013, 12:00
מקום:
חדר 337, בניין טאוב למדעי המחשב
קישור:
http://www.geometrie.tuwien.ac.at/vaxman/

Polyhedral meshes are meshes in which all faces are planar. These meshes are of paramount importance to architectural and industrial geometry, as such faces can be assumed with ease with plates of glass or wood. Furthermore, polyhedral meshes are considered as a discrete counterpart of continuous conjugate-parametrized surfaces. I will talk about methods to design such meshes by generalizing known methods from triangular-mesh processing, such as subdivision and deformation, and means to explore the shape spaces of such meshes with a given topology.

• ### TCE Talk Series - Talk III: Computer Architecture

דובר:
אלכסנדרו איסופ (אונ' דלפט לטכנולוגיה)
תאריך:
יום שני, 27.5.2013, 10:00
מקום:
חדר 337, בניין טאוב למדעי המחשב

This series of talks focuses on the research and education conducted by the PDS group in recent years, on topics such as grid and cloud computing, systems for massively multiplayer online games, big data, and gamification of higher education.

Our research focuses on the modeling, the design, the implementation, and the analysis of parallel and distributed systems and algorithms. Our research is fundamental in that we aim to develop and evaluate generic methods and techniques, and application-driven in that the research is motivated by application areas. Most of our research is experimental: we try to build prototypes of systems, preferably used in the real world, to demonstrate the quality of the proposed solutions. Our education focuses on the design and delivery of higher education units, such as B.Sc. and M.Sc.-level courses, and on the design of novel teaching techniques for a new, multi-cultural generation of students. We validate our teaching techniques experimentally, by gradually deploying them in the classroom.

The research part of our talks focuses on:
- New approaches for performance evaluation and benchmarking of IaaS clouds, in the lecture "IaaS Cloud Benchmarking: Approaches, Challenges, and Experience"
- Building distributed systems to support online games with massive player counts, in the lecture "Massivizing Social Games: Distributed Computing Challenges and High Quality Time"
- Exploring scheduling in IaaS clouds, in the lecture "Scheduling in IaaS Cloud Computing Environments: Anything New?"
- An empirical exploration of big data processing, in the lecture "A TU Delft Perspective on Big Data: Machine-Level Graph Processing and Time-Based Data Analytics"
The education part of our talks focuses on:
- Gamification as a technique for higher education, in the lecture "Gamification: Playful Teaching for Generation-X/-Y/-Z/…"

Bio
Alexandru Iosup is currently an Assistant Professor with the Parallel and Distributed Systems Group at TU Delft. He has received in 2009 his Ph.D. in Computer Science from the Delft University of Technology (TU Delft), the Netherlands. He was a visiting scholar at U. Wisconsin-Madison, U. Innsbruck, and U. California-Berkeley in the summers of 2006, 2008, and 2010, respectively. In 2011, Dr. Iosup has received a Veni grant (the Dutch equivalent of the US NSF CAREER.) He is the author of over 50 refereed scientific publications and have received several awards and distinctions, including best paper awards at IEEE CCGrid 2010, Euro-Par 2009, and IEEE P2P 2006. He has co-founded the Grid Workloads Archive; and the Peer-to-Peer, the Game, and the Failure Trace Archives, all of which provide open access to workload and resource operation traces from large-scale distributed computing environments. His long-term research interests are in the area of distributed computing systems and their applications (keywords: cloud computing, grid computing, peer-to-peer systems, scientific computing, massively multiplayer online games, scheduling, scalability, reliability, performance evaluation, workload characterization).

The lectures will be given in English.

• ### Haifux Club: Resource Management in Linux

דובר:
רמי רוזן
תאריך:
יום שני, 27.5.2013, 18:30
מקום:
טאוב 6
קישור:
http://haifux.org/

1. Resource management in Linux
2. Kernel Namespaces implementation (kernel 3.8)
3. Kernel Namespaces as an infrastructure for process virtualizaton

- Network namespaces and pid namespaces kernel implementation
- System calls for namespaces
- usage examples - creating linux namespaces in user space and attaching process to these namespaces

4. cgroup kernel implementation

- cgroup VFS
- cgroup filesystem ops for handling cgroups (create/attach processes, cgroup subsystem VFS specific operations, etc) examples
- The cgroup release agent and the notification API + examples
- Memory controller (memcg) example (disabling oom killer)
- Two networking controllers examples
- linbvgroup-tools + examples

5. Checkpoint/Restart in brief

• ### Pixel Club: On SIFT and their Scales

דובר:
ויקי מייזלס (הנדסת חשמל, טכניון)
תאריך:
יום רביעי, 29.5.2013, 11:30
מקום:
חדר 1061, בניין מאייר, הפקולטה להנדסת חשמל

Scale invariant feature detectors often find stable scales in only a few image pixels. Consequently, methods for feature matching typically choose one of two extreme options: matching a sparse set of scale invariant features, or dense matching using arbitrary scales. In this thesis we turn our attention to the overwhelming majority of pixels, those where stable scales are not found by standard techniques. We ask, is scale-selection necessary for these pixels, when dense, scale-invariant matching is required and if so, how can it be achieved? We make the following contributions: (i) We show that features computed over different scales, even in low-contrast areas, can be different; selecting a single scale, arbitrarily or otherwise, may lead to poor matches when the images have different scales. (ii) We show that representing each pixel as a set of SIFTs, extracted at multiple scales, allows for far better matches than single-scale descriptors, but at a computational price. Finally, (iii) we demonstrate that each such set may be accurately represented by a low-dimensional, linear subspace. A subspace to-point mapping may further be used to produce a novel descriptor representation, the Scale-Less SIFT (SLS), as an alternative to single-scale descriptors. These claims are verified by quantitative and qualitative tests, demonstrating significant improvements over existing methods.

• ### Cost Aware Fault Recovery in Clouds

דובר:
אסף ישראל, הרצאה סמינריונית למגיסטר
תאריך:
יום רביעי, 5.6.2013, 15:30
מקום:
טאוב 601
מנחה:
Prof. Danny Raz

Maintaining high availability of Ifrastructure-as-a-Service services at a reasonable cost is a challenging task that received recent attention due to the growing popularity of Cloud computing as a preferred means of affordable IT outsourcing. In large data-centers, faults are prone to happen and thus the only reasonable cost-effective method of providing high availability of services is an SLA aware recovery plan; that is, a mapping of the service VMs onto backup machines where they can be executed in case of a failure. The recovery process may benefit from powering on some of these machines in advance, since redeployment on powered machines is much faster. However, this comes with an additional maintenance cost, so the real problem is how to balance between the expected recovery time improvement and the cost of machines activation. We model this problem as an offline optimization problem and present a bicriteria approximation algorithm for it. While this is the first performance guaranteed algorithm for this problem, it is somewhat complex to implement in practice. Thus, we further present a much simpler and practical heuristic based on a greedy approach. We evaluate the performance of this heuristic over real data-center data, and show that it performs well in terms of scale, hierarchical faults and variant costs. Our results indicate that our scheme can reduce the overall recovery costs by 10-15% when compared to currently used approaches. We also show that fault recovery cost aware VM placement may farther help reducing the expected recovery costs, as it can reduce the backup machine activations costs.

• ### TCE Talk Series - Talk IV: Computer Architecture

דובר:
אלכסנדרו איסופ (אונ' דלפט לטכנולוגיה)
תאריך:
יום חמישי, 6.6.2013, 10:00
מקום:
חדר 337, בניין טאוב למדעי המחשב

This series of talks focuses on the research and education conducted by the PDS group in recent years, on topics such as grid and cloud computing, systems for massively multiplayer online games, big data, and gamification of higher education.

Our research focuses on the modeling, the design, the implementation, and the analysis of parallel and distributed systems and algorithms. Our research is fundamental in that we aim to develop and evaluate generic methods and techniques, and application-driven in that the research is motivated by application areas. Most of our research is experimental: we try to build prototypes of systems, preferably used in the real world, to demonstrate the quality of the proposed solutions. Our education focuses on the design and delivery of higher education units, such as B.Sc. and M.Sc.-level courses, and on the design of novel teaching techniques for a new, multi-cultural generation of students. We validate our teaching techniques experimentally, by gradually deploying them in the classroom.

The research part of our talks focuses on:
- New approaches for performance evaluation and benchmarking of IaaS clouds, in the lecture "IaaS Cloud Benchmarking: Approaches, Challenges, and Experience"
- Building distributed systems to support online games with massive player counts, in the lecture "Massivizing Social Games: Distributed Computing Challenges and High Quality Time"
- Exploring scheduling in IaaS clouds, in the lecture "Scheduling in IaaS Cloud Computing Environments: Anything New?"
- An empirical exploration of big data processing, in the lecture "A TU Delft Perspective on Big Data: Machine-Level Graph Processing and Time-Based Data Analytics"
The education part of our talks focuses on:
- Gamification as a technique for higher education, in the lecture "Gamification: Playful Teaching for Generation-X/-Y/-Z/…"

Bio
Alexandru Iosup is currently an Assistant Professor with the Parallel and Distributed Systems Group at TU Delft. He has received in 2009 his Ph.D. in Computer Science from the Delft University of Technology (TU Delft), the Netherlands. He was a visiting scholar at U. Wisconsin-Madison, U. Innsbruck, and U. California-Berkeley in the summers of 2006, 2008, and 2010, respectively. In 2011, Dr. Iosup has received a Veni grant (the Dutch equivalent of the US NSF CAREER.) He is the author of over 50 refereed scientific publications and have received several awards and distinctions, including best paper awards at IEEE CCGrid 2010, Euro-Par 2009, and IEEE P2P 2006. He has co-founded the Grid Workloads Archive; and the Peer-to-Peer, the Game, and the Failure Trace Archives, all of which provide open access to workload and resource operation traces from large-scale distributed computing environments. His long-term research interests are in the area of distributed computing systems and their applications (keywords: cloud computing, grid computing, peer-to-peer systems, scientific computing, massively multiplayer online games, scheduling, scalability, reliability, performance evaluation, workload characterization).

The lectures will be given in English.

• ### TCE Talk Series - Talk I: Computer Architecture (4 hours)

דובר:
פרופ' ייל פת (אונ' טקסס באוסטין)
תאריך:
יום חמישי, 13.6.2013, 14:30
מקום:
חדר 165, בניין מאייר, הפקולטה להנדסת חשמל

Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

Course Details:

Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

Bio:
Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

The lectures will be given in English.

Academic credit for registered students (exam required).

The next talks in this series will be held as following:
Talk II: Friday, June 14th, 09:00 (3 hours)
Talk III: Thursday, June 20th, 14:30 (4 hours)
Talk IV: Friday, June 21st, 09:00 (3 hours)

• ### TCE Talk Series - Talk II: Computer Architecture (3 hours)

דובר:
פרופ' ייל פת (אונ' טקסס באוסטין)
תאריך:
יום שישי, 14.6.2013, 09:00
מקום:
חדר 165, בניין מאייר, הפקולטה להנדסת חשמל

Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

Course Details:

Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

Bio:
Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

The lectures will be given in English

Academic credit for registered students (exam required).

The next talks in this series will be held as following:
Talk III: Thursday, June 20th, 14:30 (4 hours)
Talk IV: Friday, June 21st, 09:00 (3 hours) .

• ### TCE Talk Series - Talk III: Computer Architecture (4 hours)

דובר:
פרופ' ייל פת (אונ' טקסס באוסטין)
תאריך:
יום חמישי, 20.6.2013, 14:30
מקום:
חדר 165, בניין מאייר, הפקולטה להנדסת חשמל

Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

Course Details:

Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

Bio:
Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

The lectures will be given in English

Academic credit for registered students (exam required).

The next talks in this series will be held as following:
Talk IV: Friday, June 21st, 09:00 (3 hours)

• ### TCE Talk Series - Talk IV: Computer Architecture (3 hours)

דובר:
פרופ' ייל פת (אונ' טקסס באוסטין)
תאריך:
יום שישי, 21.6.2013, 09:00
מקום:
חדר 165, בניין מאייר, הפקולטה להנדסת חשמל

Using computers to solve problems requires starting with a natural language formulation of the problem and systematically transforming it until one has a machine language (ISA) specification of the problem (i.e., a program). This then is executed on the implementation hardware. As Moore's Law continues to provide more and more transistors on a chip (50 billion transistors in a few years), application specialists continue to think up more and more applications that require additional processing capability. The ISA is the interface between the software producing a program and the hardware carrying it out. The ISA is implemented by a microarchitecture that is constrained by trade-offs such as performance, power consumption, cost, reliability, availability, etc. In this course, we will examine some of the choices and tradeoffs.

Course Details:

Lecture I – A science of tradeoffs, transformation hierarchy, microarchitecture view. The algorithm, compiler, microarchitecture, physical view , tradeoffs in the ISA, microarchitecture and at the system level , speculation, the value of numbers.

Lecture II – Run-time (evolution of the microprocessor, branch prediction, trace cache, MT, SMT, SSMT, L2 miss activity), Compile-time (block-structured ISA, fast track/slow track, wish branches, braids and more).

Lecture III – Uniprocessor (SIMD, VLIW, DAE, HPS, Data Flow, Multiprocessor (tightly coupled vs loosely coupled), metrics (speedup, efficiency, redundancy, utilization), Amdahl's Law, interconnection structures, memory consistency, cache coherence.

Lecture IV – Floating point arithmetic (because every so often the computer has to compute), retrospective on RISC (because it has been greatly misunderstood), future directions (Morphcore, breaking the layers, dark silicon), and remaining questions.

Bio:
Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, advising PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his breakaway approach, "Introduction to Computing Systems: from bits and gates to C and beyond," co-authored with Prof. Sanjay Patel of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide.

The lectures will be given in English

Academic credit for registered students (exam required).