Prof. Israel Koren (University of Massachusetts, Amherst)
The benefits of Asymmetric Multicore Processors (AMPs) vs. their symmetric counterparts highly depend on the thread scheduling followed. Since the computing needs of threads often vary during their execution, a fixed thread-to-core assignment is sub-optimal. Reassigning threads to cores (e.g., thread swapping) when a thread starts a new program phase (with different computational needs), can significantly improve the energy efficiency of AMPs.
Although identifying phase changes in the threads is not difficult, determining the best thread-to-core assignment is challenging.
Furthermore, the problem of thread reassignment is aggravated by the multiple power states that may be available in the cores. Therefore, besides choosing the best core-type for the current program phase, a good thread scheduling scheme should also determine the appropriate voltage/frequency levels of the cores to achieve maximum performance/power benefits.
In this presentation, we describe a novel technique to dynamically assess the program phase needs and determine whether swapping threads between core-types and/or changing the voltage/frequency levels (DVFS) of the cores will result in higher throughput/Watt. This is achieved by predicting the expected throughput/Watt of the current program phase at different voltage/frequency levels on all the available core-types in the AMP.
We show that the benefits from thread swapping and DVFS are orthogonal, demonstrating the potential of the proposed scheme to achieve significant benefits by seamlessly combining the two.
We illustrate our approach using a dual-core High-Performance (HP)/Low-Power (LP) AMP with two power states each.
Our results show that the proposed scheme achieves a throughput/Watt improvement of about 27.2% when compared to a static baseline heterogeneous multicore, 13.7% when compared to the baseline multicore with swap-only capability and, 8% when compared to the baseline with DVFS-only.
Israel Koren is a Professor of Electrical and Computer Engineering at the University of Massachusetts, Amherst and a fellow of the IEEE.
He has been a consultant to companies like IBM, Analog Devices, Intel, AMD and National Semiconductors. His research interests include Fault-Tolerant systems, secure cryptographic devices, VLSI yield and reliability, Computer architecture and computer arithmetic. He publishes extensively and has over 250 publications in refereed journals and conferences. He is the author of the textbook "Computer Arithmetic Algorithms," 2nd Edition, A.K. Peters, Ltd., 2002, and a co-author of the textbook "Fault Tolerant Systems," Morgan-Kaufman, 2007.