Jose F. Martinez (Cornell University)
Tuesday, 30.10.2012, 13:30
As each technology generation brings additional transistors, the computer industry hopes to convert these into performance growth by stamping out a greater number of cores on a die. On the one hand, in many environments, that seems like a lot of hope. On the other hand, architecture researchers have grown almost allergic to "complex" alternatives, which history has shown can quickly fall off the cliff of diminishing returns.
A fundamental hurdle to bettering architectures may lie in the very perception of complexity. Many past and current architectures are indeed complex, but often in an unsophisticated way. Hardware designs tend to be very human-centric: decisions are primarily taken by human beings at design time, based almost exclusively on their experience and ability. Unsurprisingly, the operation of the adopted mechanisms is typically confined to what a human can readily understand; and the end product often falls short in potentially important capabilities, such as the ability to plan ahead, to act successfully in previously unseen states, or to improve automatically with experience.
At Cornell University, we are investigating architectures that possess and exploit such capabilities, primarily by leveraging machine learning technology. Our approach encourages the designer to focus more on the system variables and constraints that may play a role in realizing a performance objective, rather than formulating exactly how the hardware should accomplish such an objective. In this way, we have, for example, devised self-optimizing memory controllers that automatically adapt to changing software demands, delivering higher performance in ways that may be unintuitive to a human. Our ultimate goal is better computers through a more productive use of human ingenuity. Bio: Prof. Martinez earned MS (1999) and Ph.D. (2002) degrees in computer science from the University of Illinois at Urbana-Champaign, where he returned in November of last year to receive the department's inaugural Distinguished Educator Award. He is a senior member of the ACM and the IEEE, Acting Editor in Chief of IEEE Computer Architecture Letters, as well as Associate Editor of ACM Trans. on Computer Architecture and Code Optimization.